100 lines
2.2 KiB
ArmAsm
100 lines
2.2 KiB
ArmAsm
/*
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* Copyright (c) 2020 Institute of Parallel And Distributed Systems (IPADS), Shanghai Jiao Tong University (SJTU)
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* OS-Lab-2020 (i.e., ChCore) is licensed under the Mulan PSL v1.
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* You can use this software according to the terms and conditions of the Mulan PSL v1.
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* You may obtain a copy of Mulan PSL v1 at:
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* http://license.coscl.org.cn/MulanPSL
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
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* PURPOSE.
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* See the Mulan PSL v1 for more details.
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*/
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// Copyright 2016 The Fuchsia Authors
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// Copyright (c) 2014, Google Inc. All rights reserved
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//
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// Use of this source code is governed by a MIT-style
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// license that can be found in the LICENSE file or at
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// https://opensource.org/licenses/MIT
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#include <common/asm.h>
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BEGIN_FUNC(flush_idcache)
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ic iallu
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dsb nsh
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isb
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dsb sy
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mrs x0, clidr_el1
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and x3, x0, #0x7000000
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lsr x3, x3, #23
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cbz x3, finished
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mov x10, #0
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loop1:
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add x2, x10, x10, lsr #1
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lsr x1, x0, x2
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and x1, x1, #7
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cmp x1, #2
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b.lt skip
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msr csselr_el1, x10
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isb
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mrs x1, ccsidr_el1
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and x2, x1, #7
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add x2, x2, #4
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mov x4, #0x3ff
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and x4, x4, x1, lsr #3
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clz w5, w4
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mov x7, #0x7fff
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and x7, x7, x1, lsr #13
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loop2:
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mov x9, x4
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loop3:
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lsl x6, x9, x5
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orr x11, x10, x6
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lsl x6, x7, x2
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orr x11, x11, x6
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dc cisw, x11
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subs x9, x9, #1
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b.ge loop3
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subs x7, x7, #1
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b.ge loop2
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skip:
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add x10, x10, #2
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cmp x3, x10
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b.gt loop1
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finished:
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mov x10, #0
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msr csselr_el1, x10
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dsb sy
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isb
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ret
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END_FUNC(flush_idcache)
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BEGIN_FUNC(set_ttbr0_el1)
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msr ttbr0_el1, x0
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dsb sy
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tlbi vmalle1is
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dsb sy
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isb
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ret
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END_FUNC(set_ttbr0_el1)
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/*
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* this is a simple implementation for now.
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* Note that tlbi is TLB invalidation instruction and vmalle1is is its arguement.
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* This function can flush all the TLB on all the (inner sharable) cores.
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* Different from x86 architecture, IPI is not required.
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*/
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BEGIN_FUNC(flush_tlb)
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tlbi vmalle1is
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dsb sy
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isb
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ret
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END_FUNC(flush_tlb)
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