59 lines
2.5 KiB
C
59 lines
2.5 KiB
C
/*
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MIT License
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Copyright (c) 2018 Sergey Matyukevich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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*/
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/*
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* ChCore refers to
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* https://github.com/s-matyukevich/raspberry-pi-os/blob/master/docs/lesson01/rpi-os.md
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* for the min-uart init process.
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*/
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#pragma once
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/* This peripheral mapped offset is specific to BCM2837 */
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#define PHYSADDR_OFFSET 0x3F000000UL
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/* BCM2835 and BCM2837 define the same offsets */
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#define GPFSEL1 (PHYSADDR_OFFSET + 0x00200004)
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#define GPSET0 (PHYSADDR_OFFSET + 0x0020001C)
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#define GPCLR0 (PHYSADDR_OFFSET + 0x00200028)
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#define GPPUD (PHYSADDR_OFFSET + 0x00200094)
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#define GPPUDCLK0 (PHYSADDR_OFFSET + 0x00200098)
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#define AUX_ENABLES (PHYSADDR_OFFSET + 0x00215004)
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#define AUX_MU_IO_REG (PHYSADDR_OFFSET + 0x00215040)
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#define AUX_MU_IER_REG (PHYSADDR_OFFSET + 0x00215044)
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#define AUX_MU_IIR_REG (PHYSADDR_OFFSET + 0x00215048)
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#define AUX_MU_LCR_REG (PHYSADDR_OFFSET + 0x0021504C)
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#define AUX_MU_MCR_REG (PHYSADDR_OFFSET + 0x00215050)
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#define AUX_MU_LSR_REG (PHYSADDR_OFFSET + 0x00215054)
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#define AUX_MU_MSR_REG (PHYSADDR_OFFSET + 0x00215058)
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#define AUX_MU_SCRATCH (PHYSADDR_OFFSET + 0x0021505C)
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#define AUX_MU_CNTL_REG (PHYSADDR_OFFSET + 0x00215060)
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#define AUX_MU_STAT_REG (PHYSADDR_OFFSET + 0x00215064)
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#define AUX_MU_BAUD_REG (PHYSADDR_OFFSET + 0x00215068)
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void early_put32(unsigned long int addr, unsigned int ch);
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unsigned int early_get32(unsigned long int addr);
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void delay(unsigned long time);
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