34 lines
1.2 KiB
C
34 lines
1.2 KiB
C
/*
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* Copyright (c) 2020 Institute of Parallel And Distributed Systems (IPADS), Shanghai Jiao Tong University (SJTU)
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* OS-Lab-2020 (i.e., ChCore) is licensed under the Mulan PSL v1.
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* You can use this software according to the terms and conditions of the Mulan PSL v1.
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* You may obtain a copy of Mulan PSL v1 at:
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* http://license.coscl.org.cn/MulanPSL
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
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* PURPOSE.
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* See the Mulan PSL v1 for more details.
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*/
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#pragma once
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#include <common/vars.h>
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/* raspi3 config */
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#define PLAT_CPU_NUM 4
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// Timers interrupt control registers
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#define IMER_IRQCNTL_BASE (KBASE + 0x40000040)
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#define CORE0_TIMER_IRQCNTL (IMER_IRQCNTL_BASE + 0x0)
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#define CORE1_TIMER_IRQCNTL (IMER_IRQCNTL_BASE + 0x4)
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#define CORE2_TIMER_IRQCNTL (IMER_IRQCNTL_BASE + 0x8)
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#define CORE3_TIMER_IRQCNTL (IMER_IRQCNTL_BASE + 0xc)
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#define INT_SRC_TIMER3 0x008
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// IRQ & FIQ source registers
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#define IRQ_BASE (KBASE + 0x40000060)
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#define CORE0_IRQ (IRQ_BASE + 0x0)
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#define CORE1_IRQ (IRQ_BASE + 0x4)
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#define CORE2_IRQ (IRQ_BASE + 0x8)
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#define CORE3_IRQ (IRQ_BASE + 0xc)
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