118 lines
6.0 KiB
C
118 lines
6.0 KiB
C
/*
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* Copyright (c) 2020 Institute of Parallel And Distributed Systems (IPADS), Shanghai Jiao Tong University (SJTU)
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* OS-Lab-2020 (i.e., ChCore) is licensed under the Mulan PSL v1.
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* You can use this software according to the terms and conditions of the Mulan PSL v1.
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* You may obtain a copy of Mulan PSL v1 at:
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* http://license.coscl.org.cn/MulanPSL
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* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR
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* PURPOSE.
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* See the Mulan PSL v1 for more details.
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*/
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#pragma once
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#include <common/macro.h>
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/* ARMv8 AA64 REGISTERS */
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/* SPSR_EL1 Register aarch64 (FROM ARM-ARM C5-395) */
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/* Holds the saved process state when an exception is taken to EL1 */
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#define SPSR_EL1_N BIT(31) /* N condition flag */
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#define SPSR_EL1_Z BIT(30) /* Z condition flag */
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#define SPSR_EL1_C BIT(29) /* C condition flag */
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#define SPSR_EL1_V BIT(28) /* V condition flag */
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#define SPSR_EL1_DIT BIT(24) /* Data Independent Timing PSTATE.DIT ARMv8.4 */
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#define SPSR_EL1_UAO BIT(23) /* User Access Override PSTATE.UAO ARMv8.2 */
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#define SPSR_EL1_PAN BIT(22) /* Privileged Access Never PSTATE.PAN ARMv8.1 */
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#define SPSR_EL1_SS BIT(21) /* Software Step PSTATE.SS */
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#define SPSR_EL1_IL BIT(20) /* Illegal Execution state PSTATE.IL */
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#define SPSR_EL1_DEBUG BIT(9) /* Debug mask */
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#define SPSR_EL1_SERROR BIT(8) /* SERROR mask */
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#define SPSR_EL1_IRQ BIT(7) /* IRQ mask */
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#define SPSR_EL1_FIQ BIT(6) /* FIQ mask */
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#define SPSR_EL1_M BIT(4) /* Exception taken from AArch64 */
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#define SPSR_EL1_EL0t 0b0000
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#define SPSR_EL1_EL1t 0b0100
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#define SPSR_EL1_EL1h 0b0101
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/* SPSR_EL1 DEFAULT */
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#define SPSR_EL1_KERNEL SPSR_EL1_EL1h
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#define SPSR_EL1_USER SPSR_EL1_EL0t
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/* SCTLR_EL1 System Control Register aarch64 (FROM ARM-ARM D12-3081) */
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#define SCTLR_EL1_EnIA BIT(31) /* Controls enabling of pointer authentication */
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#define SCTLR_EL1_EnIB BIT(30) /* Controls enabling of pointer authentication */
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#define SCTLR_EL1_LSMAOE BIT(29) /* Load Multiple and Store Multiple Atomicity and Ordering Enable */
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#define SCTLR_EL1_nTLSMD BIT(28) /* No Trap Load Multiple and Store Multiple to Device-nGRE/Device-nGnRE/Device-nGnRnE memory */
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#define SCTLR_EL1_EnDA BIT(27) /* Controls enabling of pointer authentication */
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#define SCTLR_EL1_UCI BIT(26) /* Traps EL0 execution of cache maintenance instructions to EL1, from AArch64 state only */
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#define SCTLR_EL1_EE BIT(25) /* Endianness of data accesses at EL1, and stage 1 translation table walks in the EL1&0 translation regime */
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#define SCTLR_EL1_E0E BIT(24) /* Endianness of data accesses at EL0 */
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#define SCTLR_EL1_SPAN BIT(23) /* Set Privileged Access Never, on taking an exception to EL1 */
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#define SCTLR_EL1_IESB BIT(21) /* Implicit error synchronization event enable */
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#define SCTLR_EL1_WXN BIT(19) /* Write permission implies XN (Execute-never) */
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#define SCTLR_EL1_nTWE BIT(18) /* Traps EL0 execution of WFE instructions to EL1, from both Execution states */
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#define SCTLR_EL1_nTWI BIT(16) /* Traps EL0 execution of WFI instructions to EL1, from both Execution states */
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#define SCTLR_EL1_UCT BIT(15) /* Traps EL0 accesses to the CTR_EL0 to EL1, from AArch64 state only */
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#define SCTLR_EL1_DZE BIT(14) /* Traps EL0 execution of DC ZVA instructions to EL1, from AArch64 state only */
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#define SCTLR_EL1_EnDB BIT(13) /* Controls enabling of pointer authentication */
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#define SCTLR_EL1_I BIT(12) /* Instruction access Cacheability control, for accesses at EL0 and EL1 */
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#define SCTLR_EL1_UMA BIT(9) /* User Mask Access: Traps EL0 execution of MSR and MRS instructions that access the PSTATE.{D, A, I, F} */
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#define SCTLR_EL1_SED BIT(8) /* SETEND instruction disable. Disables SETEND instructions at EL0 using AArch32 */
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#define SCTLR_EL1_ITD BIT(7) /* IT Disable. Disables some uses of IT instructions at EL0 using AArch32 */
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#define SCTLR_EL1_nAA BIT(6) /* Non-aligned access. This bit controls generation of Alignment faults at EL1 and EL0 under certain conditions */
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#define SCTLR_EL1_CP15BEN BIT(5) /* System instruction memory barrier enable (AArch32) */
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#define SCTLR_EL1_SA0 BIT(4) /* SP Alignment check enable for EL0 */
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#define SCTLR_EL1_SA BIT(3) /* SP Alignment check */
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#define SCTLR_EL1_C BIT(2) /* Cacheability control for data accesses */
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#define SCTLR_EL1_A BIT(1) /* Alignment check enable */
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#define SCTLR_EL1_M BIT(0) /* MMU enable for EL1 and EL0 stage 1 address translation */
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#ifndef __ASM__
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/* Types of the registers */
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enum reg_type {
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X0 = 0, /* 0x00 */
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X1 = 1, /* 0x08 */
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X2 = 2, /* 0x10 */
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X3 = 3, /* 0x18 */
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X4 = 4, /* 0x20 */
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X5 = 5, /* 0x28 */
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X6 = 6, /* 0x30 */
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X7 = 7, /* 0x38 */
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X8 = 8, /* 0x40 */
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X9 = 9, /* 0x48 */
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X10 = 10, /* 0x50 */
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X11 = 11, /* 0x58 */
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X12 = 12, /* 0x60 */
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X13 = 13, /* 0x68 */
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X14 = 14, /* 0x70 */
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X15 = 15, /* 0x78 */
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X16 = 16, /* 0x80 */
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X17 = 17, /* 0x88 */
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X18 = 18, /* 0x90 */
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X19 = 19, /* 0x98 */
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X20 = 20, /* 0xa0 */
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X21 = 21, /* 0xa8 */
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X22 = 22, /* 0xb0 */
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X23 = 23, /* 0xb8 */
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X24 = 24, /* 0xc0 */
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X25 = 25, /* 0xc8 */
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X26 = 26, /* 0xd0 */
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X27 = 27, /* 0xd8 */
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X28 = 28, /* 0xe0 */
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X29 = 29, /* 0xe8 */
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X30 = 30, /* 0xf0 */
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SP_EL0 = 31, /* 0xf8 */
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ELR_EL1 = 32, /* 0x100 NEXT PC */
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SPSR_EL1 = 33, /* 0x108 */
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TPIDR_EL0 = 34
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};
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#endif /* ASMCODE */
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#define REG_NUM 35
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#define SZ_U64 8
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#define ARCH_EXEC_CONT_SIZE REG_NUM*SZ_U64 /* Cannot use sizeof in asm */
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